Import of the watch repository from Pebble

src/libos/include/mcu/cache.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+// Instruction cache and data cache are entirely separate. Therefore, you must both flush data
+// cache _and_ invalidate instruction cache for that region in order to properly execute new code.
+
+// A cache flush means the data is written out from the cache into memory. A cache invalidate
+// means the data in the cache is thrown out and will be reloaded from memory on the next access.
+// A flush does keep the data still in cache, so if you want to write out and invalidate, you want
+// to use flush_invalidate.
+
+// All cache operations MUST operate on the cache line size. You can safely flush memory that isn't
+// part of your buffer, but invalidation CAN AND WILL destroy other memory! Be very careful!
+
+// The cache line size on Cortex-M7 is 32 bytes.
+
+//! Enable instruction cache.
+void icache_enable(void);
+//! Disable instruction cache.
+void icache_disable(void);
+//! Returns whether or not ICache is enabled
+bool icache_is_enabled(void);
+//! Returns line size of ICache.
+uint32_t icache_line_size(void);
+
+//! Invalidate entire instruction cache.
+void icache_invalidate_all(void);
+//! Invalidate instruction cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void icache_invalidate(void *addr, size_t size);
+
+//! Enable data cache.
+void dcache_enable(void);
+//! Disable data cache.
+void dcache_disable(void);
+//! Returns whether or not DCache is enabled
+bool dcache_is_enabled(void);
+//! Returns line size of DCache.
+uint32_t dcache_line_size(void);
+
+//! Flush entire data cache.
+void dcache_flush_all(void);
+//! Invalidate entire data cache.
+void dcache_invalidate_all(void);
+//! Flush, then invalidate entire data cache.
+void dcache_flush_invalidate_all(void);
+
+//! Flush data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_flush(const void *addr, size_t size);
+//! Invalidate data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_invalidate(void *addr, size_t size);
+//! Flush, then invalidate data cache for `addr` for `size` bytes.
+//! `addr` and `size` should both be aligned by the cache line size.
+void dcache_flush_invalidate(const void *addr, size_t size);
+
+//! Aligns an address and size so that they are both aligned to the ICache line size, and still
+//! covers the range requested.
+void icache_align(uintptr_t *addr, size_t *size);
+//! Aligns an address and size so that they are both aligned to the DCache line size, and still
+//! covers the range requested.
+void dcache_align(uintptr_t *addr, size_t *size);
+
+//! For aligning things to work with the data cache, you will want to check what the cache line
+//! size is, and align accordingly. However, the hardware peripheral also might require a minimum
+//! alignment. So you pass the minimum alignment in bytes into `min`, and the return value is the
+//! mask you can apply to get the minimum aligned address.
+uint32_t dcache_alignment_mask_minimum(uint32_t min);

src/libos/include/mcu/fpu.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+void mcu_fpu_cleanup(void);

src/libos/include/mcu/interrupts.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+inline static bool mcu_state_is_isr(void);
+
+//! Return the priority level of the currently executing exception handler.
+//! Returns ~0 if not in an exception handler. Lower numbers mean higher
+//! priority. Anything below 0xB should not execute any FreeRTOS calls.
+inline static uint32_t mcu_state_get_isr_priority(void);
+
+bool mcu_state_are_interrupts_enabled(void);
+
+#ifdef __arm__
+#include "mcu/interrupts_arm.inl.h"
+#else
+#include "mcu/interrupts_stubs.inl.h"
+#endif

src/libos/include/mcu/interrupts_arm.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+static inline bool mcu_state_is_isr(void) {
+  return __get_IPSR() != 0;
+}
+
+static inline uint32_t mcu_state_get_isr_priority(void) {
+  uint32_t exc_number  = __get_IPSR();
+  if (exc_number == 0) {
+    return ~0;
+  }
+  // Exception numbers 0 -> 15 are "internal" interrupts and NVIC_GetPriority() expects them to be
+  // negative numbers.
+  return NVIC_GetPriority((int)exc_number - 16);
+}

src/libos/include/mcu/interrupts_stubs.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static inline bool mcu_state_is_isr(void) {
+  return false;
+}
+
+static inline uint32_t mcu_state_get_isr_priority(void) {
+  return ~0;
+}

src/libos/include/mcu/privilege.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+inline static bool mcu_state_is_thread_privileged(void);
+
+//! Update the thread mode privilege bit in the control register. Note that you
+//! must already be privileged to call this with a true argument.
+void mcu_state_set_thread_privilege(bool privilege);
+
+bool mcu_state_is_privileged(void);
+
+#ifdef __arm__
+#include "mcu/privilege_arm.inl.h"
+#else
+#include "mcu/privilege_stubs.inl.h"
+#endif

src/libos/include/mcu/privilege_arm.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define CMSIS_COMPATIBLE
+#include <mcu.h>
+
+
+//! @file privilege_arm.inl.h
+//! Helpful functions for dealing with our micros execution state.
+//!
+//! Functions in this file muck with the control register. This register is described here:
+//! http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf page 2-9
+//! We only really care about the 0th bit.
+//! [0] nPriv Defines the Thread mode privilege level
+//!           0 = Privileged
+//!           1 = Unprivileged
+//! This variable can be read in both modes, but only may be written in privileged mode.
+
+// See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/CHDIGFCA.html
+// for a more detailed explanation of these various privilege states.
+
+static inline bool mcu_state_is_thread_privileged(void) {
+  return (__get_CONTROL() & 0x1) == 0;
+}

src/libos/include/mcu/privilege_stubs.inl.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "util/attributes.h"
+
+static inline bool mcu_state_is_thread_privileged(void) {
+  return true;
+}
+
+void WEAK mcu_state_set_thread_privilege(bool privilege) {
+}
+
+bool WEAK mcu_state_is_privileged(void) {
+  return true;
+}

src/libos/include/os/assert.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "util/attributes.h"
+#include "util/likely.h"
+
+#include <stdint.h>
+
+NORETURN os_assertion_failed(const char *filename, int line);
+NORETURN os_assertion_failed_lr(const char *filename, int line, uint32_t lr);
+
+#define OS_ASSERT(expr) \
+  do { \
+    if (UNLIKELY(!(expr))) { \
+      os_assertion_failed(__FILE_NAME__, __LINE__); \
+    } \
+  } while (0)
+
+#define OS_ASSERT_LR(expr, lr) \
+  do { \
+    if (UNLIKELY(!(expr))) { \
+      os_assertion_failed_lr(__FILE_NAME__, __LINE__, lr); \
+    } \
+  } while (0)

src/libos/include/os/malloc.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stddef.h>
+
+void *os_malloc(size_t size);
+void *os_malloc_check(size_t size);
+void os_free(void *ptr);

src/libos/include/os/mutex.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+
+#include "util/list.h"
+
+struct pebble_mutex_t;
+typedef struct pebble_mutex_t PebbleMutex;
+struct pebble_recursive_mutex_t;
+typedef struct pebble_recursive_mutex_t PebbleRecursiveMutex;
+
+#define INVALID_MUTEX_HANDLE 0
+
+//! @return INVALID_MUTEX_HANDLE if failed, success otherwise.
+PebbleMutex *mutex_create(void);
+
+void mutex_destroy(PebbleMutex *handle);
+
+void mutex_lock(PebbleMutex *handle);
+
+bool mutex_lock_with_timeout(PebbleMutex *handle, uint32_t timeout_ms);
+
+void mutex_lock_with_lr(PebbleMutex *handle, uint32_t myLR);
+
+void mutex_unlock(PebbleMutex *handle);
+
+PebbleRecursiveMutex * mutex_create_recursive(void);
+
+void mutex_lock_recursive(PebbleRecursiveMutex *handle);
+
+bool mutex_lock_recursive_with_timeout(PebbleRecursiveMutex *handle, uint32_t timeout_ms);
+
+bool mutex_lock_recursive_with_timeout_and_lr(PebbleRecursiveMutex *handle,
+                                              uint32_t timeout_ms,
+                                              uint32_t LR);
+
+//! Tests if a given mutex is owned by the current task. Useful for
+//! ensuring locks are held when they should be.
+bool mutex_is_owned_recursive(PebbleRecursiveMutex *handle);
+
+void mutex_unlock_recursive(PebbleRecursiveMutex *handle);
+
+//! @return true if the calling task owns the mutex
+void mutex_assert_held_by_curr_task(PebbleMutex *handle, bool is_held);
+
+//! @return true if the calling task owns the mutex
+void mutex_assert_recursive_held_by_curr_task(PebbleRecursiveMutex *handle, bool is_held);

src/libos/include/os/tick.h

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+/*
+ * Copyright 2024 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "portmacro.h"
+
+#include <stdint.h>
+
+TickType_t milliseconds_to_ticks(uint32_t milliseconds);
+
+uint32_t ticks_to_milliseconds(TickType_t ticks);