Import of the watch repository from Pebble

third_party/nanopb/tests/site_scons/platforms/avr/avr.py

@@ -0,0 +1,26 @@
+# Compiler settings for running the tests on a simulated atmega1284.
+
+def set_avr_platform(env):
+    native = env.Clone()
+    native.Append(LIBS = ["simavr", "libelf"], CFLAGS = "-Wall -Werror -g")
+    runner = native.Program("build/run_test", "site_scons/platforms/avr/run_test.c")
+    
+    env.Replace(EMBEDDED = "AVR")
+    env.Replace(CC  = "avr-gcc",
+                CXX = "avr-g++")
+    env.Replace(TEST_RUNNER = "build/run_test")
+    env.Append(CFLAGS = "-mmcu=atmega1284 -Dmain=app_main -Os -g -Wall ")
+    env.Append(CXXFLAGS = "-mmcu=atmega1284 -Dmain=app_main -Os -Wno-type-limits")
+    env.Append(CPPDEFINES = {'PB_CONVERT_DOUBLE_FLOAT': 1, 'UNITTESTS_SHORT_MSGS': 1,
+                             '__ASSERT_USE_STDERR': 1, 'MAX_ALLOC_BYTES': 32768,
+                             'FUZZTEST_BUFSIZE': 2048})
+    env.Append(LINKFLAGS = "-mmcu=atmega1284")
+    env.Append(LINKFLAGS = "-Wl,-Map,build/avr.map")
+
+    # Build library for communicating with test runner
+    avr_io = env.Object("build/avr_io.o", "site_scons/platforms/avr/avr_io.c")
+    env.Append(LIBS = avr_io)
+    
+    # This fake define just ensures that the test runner gets build also
+    env.Depends(avr_io, runner)
+

third_party/nanopb/tests/site_scons/platforms/avr/avr_io.c

@@ -0,0 +1,91 @@
+/* This wrapper file initializes stdio to UART connection and
+ * receives the list of command line arguments.
+ */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <avr/sleep.h>
+
+#undef main
+extern int app_main(int argc, const char **argv);
+
+struct {
+    uint8_t argc;
+    char args[3][16];
+} g_args;
+
+int uart_putchar(char c, FILE *stream)
+{
+    loop_until_bit_is_set(UCSR0A, UDRE0);
+    UDR0 = c;
+    return 0;
+}
+
+int uart_getchar(FILE *stream)
+{
+    while (bit_is_clear(UCSR0A, RXC0) && bit_is_clear(UCSR0A, FE0));
+    if (UCSR0A & _BV(FE0)) return _FDEV_EOF; /* Break = EOF */
+    return UDR0;
+}
+
+FILE uart_str = FDEV_SETUP_STREAM(uart_putchar, uart_getchar, _FDEV_SETUP_RW);
+static char g_malloc_heap[8192];
+extern uint32_t __bss_end;
+
+void abort(void)
+{
+    if (__bss_end != 0xDEADBEEF)
+    {
+        fprintf(stderr, "possible stack overflow\n");
+    }
+
+    fprintf(stderr, "abort() called\n");
+    DDRB = 3;
+    PORTB = 1;
+    cli();
+    while (1) sleep_mode();
+}
+
+int main(void)
+{
+    const char *argv[4] = {"main", g_args.args[0], g_args.args[1], g_args.args[2]};
+    int status;
+    
+    UBRR0 = (8000000 / (16UL * 9600)) - 1; /* 9600 bps with default 8 MHz clock */
+    UCSR0B = _BV(TXEN0) | _BV(RXEN0);
+    
+    __malloc_heap_start = g_malloc_heap;
+    __malloc_heap_end = g_malloc_heap + sizeof(g_malloc_heap);
+
+    __bss_end = 0xDEADBEEF;
+
+    stdout = stdin = stderr = &uart_str;
+    
+    fread((char*)&g_args, 1, sizeof(g_args), stdin);
+    
+    status = app_main(g_args.argc + 1, argv);
+
+    if (__bss_end != 0xDEADBEEF)
+    {
+        status = 255;
+        fprintf(stderr, "possible stack overflow\n");
+    }
+
+    DDRB = 3;
+    if (status)
+    {
+        fprintf(stderr, "Error exit: %d\n", status);
+        PORTB = 1; // PB0 indicates error
+    }
+    else
+    {
+        PORTB = 2; // PB1 indicates success
+    }
+  
+    cli();
+    sleep_mode();
+    return status;
+}
+

third_party/nanopb/tests/site_scons/platforms/avr/run_test.c

@@ -0,0 +1,196 @@
+#include <unistd.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <stdio.h>
+#include <libgen.h>
+#include <simavr/sim_avr.h>
+#include <simavr/sim_gdb.h>
+#include <simavr/avr_ioport.h>
+#include <simavr/sim_elf.h>
+#include <simavr/avr_uart.h>
+
+static avr_t *g_avr;
+static avr_irq_t *g_uart_irq;
+
+static struct {
+    uint8_t argc;
+    char args[3][16];
+} g_args;
+static int g_args_idx;
+static bool g_uart_xon;
+static bool g_status_ok;
+
+static void uart_tx_hook(struct avr_irq_t * irq, uint32_t value, void * param)
+{
+    fputc(value, stdout);
+    fflush(stdout);
+}
+
+static bool stdin_can_read()  
+{
+  struct timeval tv;
+  fd_set fds;
+  tv.tv_sec = 0;
+  tv.tv_usec = 0;
+  FD_ZERO(&fds);
+  FD_SET(STDIN_FILENO, &fds);
+  select(STDIN_FILENO+1, &fds, NULL, NULL, &tv);
+  return (FD_ISSET(0, &fds));
+}
+
+static void avr_logger(avr_t * avr, const int level, const char * format, va_list ap)
+{
+    if ((!avr && level <= LOG_WARNING) || (avr && avr->log >= level)) {
+        vfprintf(stderr , format, ap);
+    }
+}
+
+static void uart_xon_hook(struct avr_irq_t * irq, uint32_t value, void * param)
+{
+    g_uart_xon = true;
+    int v;
+    
+    if (feof(stdin))
+    {
+        avr_raise_irq(&g_uart_irq[1], UART_INPUT_FE);
+        return;
+    }
+
+    while (g_uart_xon)
+    {
+        if (g_args_idx < sizeof(g_args))
+        {
+            v = ((char*)&g_args)[g_args_idx++];
+        }
+        else if (stdin_can_read())
+        {
+            v = fgetc(stdin);
+        }
+        else
+        {
+            break;        
+        }
+        
+        if (v != EOF)
+        {
+            avr_raise_irq(&g_uart_irq[1], v);
+        }
+        else
+        {
+            avr_raise_irq(&g_uart_irq[1], UART_INPUT_FE);
+            break;
+        }
+    }
+}
+
+static void uart_xoff_hook(struct avr_irq_t * irq, uint32_t value, void * param)
+{
+    g_uart_xon = false;
+}
+
+void init_uart()
+{
+    const char *irq_names[2] = {"8<uart_in", "8>uart_out"};
+    g_uart_irq = avr_alloc_irq(&g_avr->irq_pool, 0, 2, irq_names);
+    avr_irq_register_notify(&g_uart_irq[0], &uart_tx_hook, NULL);
+    
+    uint32_t flags = 0;
+    avr_ioctl(g_avr, AVR_IOCTL_UART_GET_FLAGS('0'), &flags);
+    flags &= ~AVR_UART_FLAG_STDIO;
+    flags &= ~AVR_UART_FLAG_POLL_SLEEP;
+    avr_ioctl(g_avr, AVR_IOCTL_UART_SET_FLAGS('0'), &flags);
+
+    avr_irq_t *src = avr_io_getirq(g_avr, AVR_IOCTL_UART_GETIRQ('0'), UART_IRQ_OUTPUT);
+    avr_irq_t *dst = avr_io_getirq(g_avr, AVR_IOCTL_UART_GETIRQ('0'), UART_IRQ_INPUT);
+    avr_connect_irq(src, &g_uart_irq[0]);
+    avr_connect_irq(&g_uart_irq[1], dst);
+    
+    avr_irq_t *xon = avr_io_getirq(g_avr, AVR_IOCTL_UART_GETIRQ('0'), UART_IRQ_OUT_XON);
+    avr_irq_t *xoff = avr_io_getirq(g_avr, AVR_IOCTL_UART_GETIRQ('0'), UART_IRQ_OUT_XOFF);
+    avr_irq_register_notify(xon, uart_xon_hook, NULL);
+    avr_irq_register_notify(xoff, uart_xoff_hook, NULL);
+}
+
+static void status_ok_hook(struct avr_irq_t * irq, uint32_t value, void * param)
+{
+    g_status_ok = value;
+}
+
+int main(int argc, char *argv[])
+{
+    avr_global_logger_set(&avr_logger);
+    g_avr = avr_make_mcu_by_name("atmega1284");
+    if (!g_avr)
+    {
+        fprintf(stderr, "avr_make_mcu_by_name failed\n");
+        return 1;
+    }
+    
+    if (argc < 2)
+    {
+        fprintf(stderr, "Usage: %s [-g] binary [args ...]\n", argv[0]);
+        return 2;
+    }
+    
+    const char *filename = argv[1];
+    bool enable_gdb = false;
+    int argc_offset = 2;
+    
+    if (strcmp(filename, "-g") == 0)
+    {
+        enable_gdb = true;
+        argc_offset = 3;
+        filename = argv[2];
+    }
+    
+    elf_firmware_t firmware = {};
+    elf_read_firmware(filename, &firmware);
+    avr_init(g_avr);
+	avr_load_firmware(g_avr, &firmware);
+	g_avr->frequency = 8000000;
+
+    if (enable_gdb)
+    {
+        g_avr->state = cpu_Stopped;
+        g_avr->gdb_port = 1234;
+        avr_gdb_init(g_avr);
+    }
+
+    init_uart();
+    
+    avr_irq_register_notify(avr_io_getirq(g_avr, AVR_IOCTL_IOPORT_GETIRQ('B'), 1), status_ok_hook, NULL);
+
+    // Pass the rest of arguments to application inside simulator
+    g_args.argc = argc - argc_offset;
+    if (g_args.argc > 3) g_args.argc = 3;
+    for (int i = 0; i < g_args.argc; i++)
+    {
+        strncpy(g_args.args[i], argv[i + argc_offset], 15);
+    }
+    
+    while (1)
+    {
+		int state = avr_run(g_avr);
+		if (state == cpu_Done)
+		    break;
+		    
+   		if (state == cpu_Crashed)
+   		{
+   		    fprintf(stderr, "CPU Crashed\n");
+			return 3;
+		}
+	}
+    
+    if (g_status_ok)
+    {
+        return 0;
+    }
+    else
+    {
+        fprintf(stderr, "Received error status from simulation\n");
+        return 5;    
+    }
+}

third_party/nanopb/tests/site_scons/platforms/mips/mips.py

@@ -0,0 +1,11 @@
+# Compiler settings for running the tests on mips-linux-gnu (big endian)
+# using qemu. Requires following packages to be installed:
+# gcc-mips-linux-gnu g++-mips-linux-gnu qemu-user
+
+def set_mips_platform(env):
+    env.Replace(EMBEDDED = "MIPS")
+    env.Replace(CC  = "mips-linux-gnu-gcc",
+                CXX = "mips-linux-gnu-g++")
+    env.Replace(TEST_RUNNER = "/usr/bin/qemu-mips")
+    env.Append(LINKFLAGS = "-static")
+    

third_party/nanopb/tests/site_scons/platforms/mipsel/mipsel.py

@@ -0,0 +1,11 @@
+# Compiler settings for running the tests on mipsel-linux-gnu using
+# qemu. Requires following packages to be installed:
+# gcc-mipsel-linux-gnu g++-mipsel-linux-gnu qemu-user
+
+def set_mipsel_platform(env):
+    env.Replace(EMBEDDED = "MIPSEL")
+    env.Replace(CC  = "mipsel-linux-gnu-gcc",
+                CXX = "mipsel-linux-gnu-g++")
+    env.Replace(TEST_RUNNER = "/usr/bin/qemu-mipsel")
+    env.Append(LINKFLAGS = "-static")
+    

third_party/nanopb/tests/site_scons/platforms/riscv64/riscv64.py

@@ -0,0 +1,11 @@
+# Compiler settings for running the tests on riscv64-linux-gnu
+# using qemu. Requires following packages to be installed:
+# gcc-riscv64-linux-gnu g++-riscv64-linux-gnu qemu-user
+
+def set_riscv64_platform(env):
+    env.Replace(EMBEDDED = "RISCV64")
+    env.Replace(CC  = "riscv64-linux-gnu-gcc",
+                CXX = "riscv64-linux-gnu-g++")
+    env.Replace(TEST_RUNNER = "/usr/bin/qemu-riscv64")
+    env.Append(LINKFLAGS = "-static")
+    

third_party/nanopb/tests/site_scons/platforms/stm32/run_test.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+BINARY=$1
+BASENAME=$(basename $1)
+shift
+ARGS=$*
+
+test X$OPENOCD_BOARD == X && export OPENOCD_BOARD=board/stm32f7discovery.cfg
+
+timeout 1200s openocd -f $OPENOCD_BOARD \
+    -c "reset_config srst_only srst_nogate connect_assert_srst" \
+    -c "init" -c "arm semihosting enable" \
+    -c "arm semihosting_cmdline $BASENAME $ARGS" \
+    -c "reset halt" \
+    -c "load_image $BINARY 0" \
+    -c "reset halt" -c "resume 0x20000040" 2>openocd.log
+
+RESULT=$?
+
+if [ "$RESULT" -ne "0" ]
+then
+    cat openocd.log >&2
+    echo >&2
+fi
+
+exit $RESULT
+
+

third_party/nanopb/tests/site_scons/platforms/stm32/stm32.py

@@ -0,0 +1,18 @@
+# Compiler settings for running the tests on a STM32 discovery board
+# Tested on the STM32F7 Discovery, but should work on pretty much
+# any STM32 with >= 128kB of RAM. To avoid wearing out the flash,
+# code is run from RAM also.
+
+def set_stm32_platform(env):
+    env.Replace(EMBEDDED = "STM32")
+    env.Replace(CC  = "arm-none-eabi-gcc",
+                CXX = "arm-none-eabi-g++")
+    env.Replace(TEST_RUNNER = "site_scons/platforms/stm32/run_test.sh")
+    env.Append(CPPDEFINES = {'FUZZTEST_BUFSIZE': 4096})
+    env.Append(CFLAGS = "-mcpu=cortex-m3 -mthumb -Os")
+    env.Append(CXXFLAGS = "-mcpu=cortex-m3 -mthumb -Os")
+    env.Append(LINKFLAGS = "-mcpu=cortex-m3 -mthumb")
+    env.Append(LINKFLAGS = "site_scons/platforms/stm32/vectors.c")
+    env.Append(LINKFLAGS = "--specs=rdimon.specs")
+    env.Append(LINKFLAGS = "-Tsite_scons/platforms/stm32/stm32_ram.ld")
+    

third_party/nanopb/tests/site_scons/platforms/stm32/stm32_ram.ld

@@ -0,0 +1,194 @@
+/* Linker script to configure memory regions. 
+ * Need modifying for a specific board. 
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+	    KEEP(*(.ramboot))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > RAM
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > RAM
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > RAM
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* Location counter can end up 2byte aligned with narrow Thumb code but
+	   __etext is assumed by startup code to be the LMA of a section in RAM
+	   which must be 4byte aligned */
+	__etext = ALIGN (4);
+
+	.data :
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+	
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

third_party/nanopb/tests/site_scons/platforms/stm32/vectors.c

@@ -0,0 +1,47 @@
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void _start();
+extern void* __StackTop;
+
+static void HardFaultHandler()
+{
+    uint32_t args[3];
+    args[0] = 2;
+    args[1] = (uint32_t)"HARDFAULT";
+    args[2] = 9;
+    
+    asm("mov r0, #5\n"
+        "mov r1, %0\n"
+        "bkpt 0x00ab"  : : "r"(args) : "r0", "r1", "memory");
+    asm("mov r12, %0\n" "mov r0, #24\n" "bkpt 0x00ab" : : "r"(0xDEADBEEF) : "r0");
+    while(1);
+}
+
+void* const g_vector_table[16] __attribute__((section(".isr_vector"))) = {
+    (void*)&__StackTop,
+    (void*)&_start,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+};
+
+
+void ramboot() __attribute__((noreturn, naked, section(".ramboot")));
+void ramboot()
+{
+    *(const void**)0xE000ED08 = g_vector_table; // SCB->VTOR
+      __asm__(
+    "msr msp, %0\n\t"
+    "bx %1" : : "r" (g_vector_table[0]),
+                "r" (g_vector_table[1]) : "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif