Import of the watch repository from Pebble

third_party/nanopb/tests/site_scons/platforms/stm32/run_test.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+BINARY=$1
+BASENAME=$(basename $1)
+shift
+ARGS=$*
+
+test X$OPENOCD_BOARD == X && export OPENOCD_BOARD=board/stm32f7discovery.cfg
+
+timeout 1200s openocd -f $OPENOCD_BOARD \
+    -c "reset_config srst_only srst_nogate connect_assert_srst" \
+    -c "init" -c "arm semihosting enable" \
+    -c "arm semihosting_cmdline $BASENAME $ARGS" \
+    -c "reset halt" \
+    -c "load_image $BINARY 0" \
+    -c "reset halt" -c "resume 0x20000040" 2>openocd.log
+
+RESULT=$?
+
+if [ "$RESULT" -ne "0" ]
+then
+    cat openocd.log >&2
+    echo >&2
+fi
+
+exit $RESULT
+
+

third_party/nanopb/tests/site_scons/platforms/stm32/stm32.py

@@ -0,0 +1,18 @@
+# Compiler settings for running the tests on a STM32 discovery board
+# Tested on the STM32F7 Discovery, but should work on pretty much
+# any STM32 with >= 128kB of RAM. To avoid wearing out the flash,
+# code is run from RAM also.
+
+def set_stm32_platform(env):
+    env.Replace(EMBEDDED = "STM32")
+    env.Replace(CC  = "arm-none-eabi-gcc",
+                CXX = "arm-none-eabi-g++")
+    env.Replace(TEST_RUNNER = "site_scons/platforms/stm32/run_test.sh")
+    env.Append(CPPDEFINES = {'FUZZTEST_BUFSIZE': 4096})
+    env.Append(CFLAGS = "-mcpu=cortex-m3 -mthumb -Os")
+    env.Append(CXXFLAGS = "-mcpu=cortex-m3 -mthumb -Os")
+    env.Append(LINKFLAGS = "-mcpu=cortex-m3 -mthumb")
+    env.Append(LINKFLAGS = "site_scons/platforms/stm32/vectors.c")
+    env.Append(LINKFLAGS = "--specs=rdimon.specs")
+    env.Append(LINKFLAGS = "-Tsite_scons/platforms/stm32/stm32_ram.ld")
+    

third_party/nanopb/tests/site_scons/platforms/stm32/stm32_ram.ld

@@ -0,0 +1,194 @@
+/* Linker script to configure memory regions. 
+ * Need modifying for a specific board. 
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+	    KEEP(*(.ramboot))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > RAM
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > RAM
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > RAM
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* Location counter can end up 2byte aligned with narrow Thumb code but
+	   __etext is assumed by startup code to be the LMA of a section in RAM
+	   which must be 4byte aligned */
+	__etext = ALIGN (4);
+
+	.data :
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+	
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

third_party/nanopb/tests/site_scons/platforms/stm32/vectors.c

@@ -0,0 +1,47 @@
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void _start();
+extern void* __StackTop;
+
+static void HardFaultHandler()
+{
+    uint32_t args[3];
+    args[0] = 2;
+    args[1] = (uint32_t)"HARDFAULT";
+    args[2] = 9;
+    
+    asm("mov r0, #5\n"
+        "mov r1, %0\n"
+        "bkpt 0x00ab"  : : "r"(args) : "r0", "r1", "memory");
+    asm("mov r12, %0\n" "mov r0, #24\n" "bkpt 0x00ab" : : "r"(0xDEADBEEF) : "r0");
+    while(1);
+}
+
+void* const g_vector_table[16] __attribute__((section(".isr_vector"))) = {
+    (void*)&__StackTop,
+    (void*)&_start,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+    (void*)&HardFaultHandler,
+};
+
+
+void ramboot() __attribute__((noreturn, naked, section(".ramboot")));
+void ramboot()
+{
+    *(const void**)0xE000ED08 = g_vector_table; // SCB->VTOR
+      __asm__(
+    "msr msp, %0\n\t"
+    "bx %1" : : "r" (g_vector_table[0]),
+                "r" (g_vector_table[1]) : "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif