From 13069b7ebded2c00e732a7f0e197beea72d541de Mon Sep 17 00:00:00 2001
From: Anthony Foxclaw <35226681+tonytins@users.noreply.github.com>
Date: Sun, 9 Feb 2020 18:43:23 -0500
Subject: [PATCH] Fixed a few old bugs

- Fixed a where the VM excuted one loop regardless of instructions.
- Use the full 32 bits if an instruction is less.
---
 src/assembler/instruction_parser.rs | 4 ++++
 src/vm.rs                           | 8 ++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/assembler/instruction_parser.rs b/src/assembler/instruction_parser.rs
index 0c9cd1a..dbd5316 100644
--- a/src/assembler/instruction_parser.rs
+++ b/src/assembler/instruction_parser.rs
@@ -35,6 +35,10 @@ impl AssemblerInstruction {
             }
         }
 
+        while results.len() < 4 {
+            results.push(0);
+        }
+
         results
     }
 
diff --git a/src/vm.rs b/src/vm.rs
index 9dfe1c8..9930d44 100644
--- a/src/vm.rs
+++ b/src/vm.rs
@@ -74,7 +74,7 @@ impl VM {
     /// various public functions.
     fn execute_instruction(&mut self) -> bool {
         if self.pc >= self.program.len() {
-            return false;
+            return true;
         }
         match self.decode_opcode() {
             Opcode::LOAD => {
@@ -84,11 +84,11 @@ impl VM {
             }
             Opcode::HLT => {
                 println!("HLT encountered");
-                return false;
+                return true;
             }
             Opcode::IGL => {
                 println!("Unrecognized opcode found! Terminating!");
-                return false;
+                return true;
             }
             Opcode::ADD => {
                 let reg1 = self.registers[self.next_8_bits() as usize];
@@ -214,7 +214,7 @@ impl VM {
                 self.heap.resize(new_end as usize, 0);
             }
         }
-        true
+        false
     }
 }