From b825931ce596080979b67575828f8f4a84a23b51 Mon Sep 17 00:00:00 2001 From: Anthony Foxclaw <35226681+tonytins@users.noreply.github.com> Date: Sun, 9 Feb 2020 16:41:13 -0500 Subject: [PATCH] Support for memory allocation - Corten now has basic support for memory allocation through with the ALOC code. --- src/assembler.rs | 5 +++++ src/assembler/instruction_parser.rs | 2 +- src/vm.rs | 21 ++++++++++++++++++++- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/src/assembler.rs b/src/assembler.rs index f4a9499..fd0a75d 100644 --- a/src/assembler.rs +++ b/src/assembler.rs @@ -44,6 +44,8 @@ pub enum Opcode { JMPF, /// Jump backward JMPB, + /// Allocate memory + ALOC, NOP, } @@ -67,6 +69,7 @@ impl From for Opcode { 14 => Opcode::LT, 15 => Opcode::JMPE, 16 => Opcode::NOP, + 17 => Opcode::ALOC, _ => Opcode::IGL, } } @@ -92,6 +95,7 @@ impl From for u8 { Opcode::GT => 14, Opcode::JMPE => 15, Opcode::NOP => 16, + Opcode::ALOC => 17, Opcode::IGL => 100, } } @@ -116,6 +120,7 @@ impl<'a> From> for Opcode { CompleteStr("lte") => Opcode::LTE, CompleteStr("lt") => Opcode::LT, CompleteStr("jmpe") => Opcode::JMPE, + CompleteStr("aloc") => Opcode::ALOC, CompleteStr("nop") => Opcode::NOP, _ => Opcode::IGL, } diff --git a/src/assembler/instruction_parser.rs b/src/assembler/instruction_parser.rs index 21b1d83..0c9cd1a 100644 --- a/src/assembler/instruction_parser.rs +++ b/src/assembler/instruction_parser.rs @@ -140,4 +140,4 @@ mod instruction_parser_test { )) ); } -} +} \ No newline at end of file diff --git a/src/vm.rs b/src/vm.rs index 6bb1595..9dfe1c8 100644 --- a/src/vm.rs +++ b/src/vm.rs @@ -8,7 +8,9 @@ pub struct VM { pc: usize, /// The byte of the program being ran pub program: Vec, - /// The remainer of the module used in the division opcode + /// Memory allocation + heap: Vec, + /// The remainder of the module used in the division opcode remainder: u32, /// The result of the last comparison operation equal_flag: bool, @@ -21,6 +23,7 @@ impl VM { registers: [0; 32], pc: 0, program: vec![], + heap: vec![], remainder: 0, equal_flag: false, } @@ -204,6 +207,12 @@ impl VM { self.next_8_bits(); self.next_8_bits(); } + Opcode::ALOC => { + let reg = self.next_8_bits() as usize; + let bytes = self.registers[reg]; + let new_end = self.heap.len() as i32 + bytes; + self.heap.resize(new_end as usize, 0); + } } true } @@ -260,6 +269,16 @@ mod vm_tests { assert_eq!(vm.registers[2], 2); } + #[test] + fn test_aloc_opcode() + { + let mut vm = get_test_vm(); + vm.registers[0] = 1024; + vm.program = vec![17, 0, 0, 0]; + vm.run_once(); + assert_eq!(vm.heap.len(), 1024); + } + #[test] fn test_eq_opcode() { let mut vm = get_test_vm();