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A register-based RISC-style virtual machine written written in Rust.

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Anthony Foxclaw 1cc7b2ec6c Merge pull request #2 from tonytins/features/paser This is the second last part of the assembly parser. It simply adds functionality to the HLT instruction and preliminary support for memory allocation has been added. ## Removal of MIPs While I will be keeping up with the tutorial, the MIPs ISA will no longer be the target goal after discovering that they shutdown their Open Initiative program. But it's just one of many derivatives RISC which is a open design and many famous RISC ISAs, such Power and SPARK, are themselves open. ## Fixes - The VM now executes the whole program until it's stopped. - An instruction that isn't the full 32bit width is now padded.		2020-02-09 20:12:15 -05:00
.github/workflows	Tweaked Github CI	2020-02-08 17:00:18 -05:00
docs	We're just a RISC virtual machine	2020-02-09 19:33:00 -05:00
src	Fixed a few old bugs	2020-02-09 18:43:23 -05:00
.gitignore	Initial source commit	2020-02-06 16:37:23 -05:00
.travis.yml	Initial source commit	2020-02-06 16:37:23 -05:00
appveyor.yml	Initial source commit	2020-02-06 16:37:23 -05:00
Cargo.lock	Initial start on assembly parser	2020-02-07 21:10:16 -05:00
Cargo.toml	Initial start on assembly parser	2020-02-07 21:10:16 -05:00
LICENSE	Initial source commit	2020-02-06 16:37:23 -05:00
README.md	We're just a RISC virtual machine	2020-02-09 19:33:00 -05:00