Commit graph

33 commits

Author SHA1 Message Date
Tony Bark
872a250192 Changed required Rust version to edition 2022-05-07 18:24:56 -04:00
Tony Bark
613a65d4cf Changed license from MPL to BSD 3 Clause
- Patch number now uses three digits
- Updated edition from 2018 to 2021
2022-05-07 18:15:43 -04:00
Tony Bark
88c3162fe2
Remove Appveyor 2021-05-09 16:17:40 -04:00
Tony Bark
aaf6455762 An update!
Just minor tweaks and slight updates.
2021-05-09 15:03:45 -04:00
Anthony Foxclaw
1cc7b2ec6c
Merge pull request #2 from tonytins/features/paser
This is the second last part of the assembly parser. It simply adds functionality to the HLT instruction and preliminary support for memory allocation has been added.

## Removal of MIPs

While I will be keeping up with the tutorial, the MIPs ISA will no longer be the target goal after discovering that they shutdown their Open Initiative program. But it's just one of many derivatives RISC which is a open design and many famous RISC ISAs, such Power and SPARK, are themselves open.

## Fixes

- The VM now executes the whole program until it's stopped.
- An instruction that isn't the full 32bit width is now padded.
2020-02-09 20:12:15 -05:00
Anthony Foxclaw
4dfb99568f We're just a RISC virtual machine 2020-02-09 19:33:00 -05:00
Anthony Foxclaw
13069b7ebd Fixed a few old bugs
- Fixed a where the VM excuted one loop regardless of instructions.
- Use the full 32 bits if an instruction is less.
2020-02-09 18:43:23 -05:00
Anthony Foxclaw
b825931ce5 Support for memory allocation
- Corten now has basic support for memory allocation through with the ALOC code.
2020-02-09 16:41:13 -05:00
Anthony Foxclaw
86f060e0f5 Implemented HLT instruction
- Instructions are now detected automatically based on context
- Since MIPs can't decide if it wants to be open or not, Corten will be aiming to be more of a RISC-V VM in the long term.
2020-02-09 15:16:38 -05:00
Anthony Foxclaw
76af517a49 Tweaked Github CI 2020-02-08 17:00:18 -05:00
Anthony Foxclaw
17ab034784 Merge pull request #1 from tonytins/features/paser
This is the first part of the MIPs assembly language parser. At the moment, this mostly serves as a proof-of-concept and is only capable of the LOAD instruction.
2020-02-08 16:58:44 -05:00
Anthony Foxclaw
b90b5c22bf Fixed up READMEs 2020-02-08 16:21:41 -05:00
Anthony Foxclaw
317feb9188 Minor fixes to the code 2020-02-08 15:36:04 -05:00
Anthony Foxclaw
853188b010 Fixed bug with VM assigning wrong opcode
- Fixed a bug with VM assigning wrong opcode. After doing a little digging into the Iridium 1 source code (skipping to the next part of the tutorial), I discovered I had to have implement from() function in both directions. I.e. the Opcode outputs integer and integer outputs an Opcode. Derp moment in retrospective since I already had it done for the former but this is a learning experience.
- Moved Opcode enum to assembler module.
2020-02-08 15:14:37 -05:00
Anthony Foxclaw
afb68e46b3 Finished assembler paser
The assembler parser is finished and all tests do pass but the "load" command keeps pointing to "sub" for some reason.
2020-02-07 23:53:59 -05:00
Anthony Foxclaw
fe69c0d0c8 Implemented more of the assembler 2020-02-07 22:33:36 -05:00
Anthony Foxclaw
4bfde58cc5 Wrote AssemblerInstruction and Program parser 2020-02-07 21:49:56 -05:00
Anthony Foxclaw
1af8f089c3 Initial start on assembly parser 2020-02-07 21:10:16 -05:00
Anthony Foxclaw
95272a3472 Updated spec page 2020-02-07 02:17:59 -05:00
Anthony Foxclaw
75465c6a20 Fixed mis-numbering of opcodes
This bug was intentionally kept in order to make sure everything ran flawlessly regardless.
2020-02-07 01:01:39 -05:00
Anthony Foxclaw
d63bedda7c Added version to REPL 2020-02-07 00:02:43 -05:00
Anthony Foxclaw
263686902b REPL!
- Created a basic REPL that accepts hex code
- Commented a lot of the code
2020-02-06 23:13:00 -05:00
Anthony Foxclaw
717c99a4a6 Finished porting over the unit tests 2020-02-06 22:10:21 -05:00
Anthony Foxclaw
4822f5e00b Implemented equality checks
- Ported over most of the unit tests for the checks from Iridium 1
2020-02-06 22:05:48 -05:00
Anthony Foxclaw
2564b650ff Initial start on equality checks 2020-02-06 21:40:09 -05:00
Anthony Foxclaw
75f814a99f Fixed README links 2020-02-06 20:43:19 -05:00
Anthony Foxclaw
850d8b4ead Rereorganized README for docs 2020-02-06 20:39:19 -05:00
Anthony Foxclaw
c1bdbc78c5 Rearranaged opcode order
- Rearranaged opcodes to match Iridium's
- Grabbed the get_test_vm() function from the Iridium 1 source to keep up with the tutorial
- Specifications page with details regarding Iridium and Corten's instruction set list
2020-02-06 19:57:38 -05:00
Anthony Foxclaw
ee08374252 Implemented jump opcode 2020-02-06 18:02:09 -05:00
Anthony Foxclaw
6dd33396f0 Added Jump opcode
- And fixed a oversight in the match statement while I was at it.
2020-02-06 17:42:51 -05:00
Anthony Foxclaw
223ce4c1bd Finished LOAD, ADD, HUL and DIV implementation 2020-02-06 17:40:43 -05:00
Anthony Foxclaw
d1340fe9fc Initial start on LOAD, ADD, HUL and DIV opcodes 2020-02-06 16:47:01 -05:00
Anthony Foxclaw
08b16dae6b Initial source commit 2020-02-06 16:37:23 -05:00