This is the second last part of the assembly parser. It simply adds functionality to the HLT instruction and preliminary support for memory allocation has been added.
## Removal of MIPs
While I will be keeping up with the tutorial, the MIPs ISA will no longer be the target goal after discovering that they shutdown their Open Initiative program. But it's just one of many derivatives RISC which is a open design and many famous RISC ISAs, such Power and SPARK, are themselves open.
## Fixes
- The VM now executes the whole program until it's stopped.
- An instruction that isn't the full 32bit width is now padded.
- Instructions are now detected automatically based on context
- Since MIPs can't decide if it wants to be open or not, Corten will be aiming to be more of a RISC-V VM in the long term.
This is the first part of the MIPs assembly language parser. At the moment, this mostly serves as a proof-of-concept and is only capable of the LOAD instruction.
- Fixed a bug with VM assigning wrong opcode. After doing a little digging into the Iridium 1 source code (skipping to the next part of the tutorial), I discovered I had to have implement from() function in both directions. I.e. the Opcode outputs integer and integer outputs an Opcode. Derp moment in retrospective since I already had it done for the former but this is a learning experience.
- Moved Opcode enum to assembler module.
- Rearranaged opcodes to match Iridium's
- Grabbed the get_test_vm() function from the Iridium 1 source to keep up with the tutorial
- Specifications page with details regarding Iridium and Corten's instruction set list
